Compact and Fast Multiplier Using Dual Array Tree Structure
نویسندگان
چکیده
In this papcr, a parallel multiplier topology with compact area and fast speed is presented. This new architccturc includcs dual partial product arrays, which is divided from oncpartial product plane ofaconventional array multiplier. Due to parallel operation of this proposed dual array, multiplication speed is increased twice. Outputs of both arrays arc summed with a binary trcc addcr, whilc each partial product array is made with full addcrs. This proposed multiplier fabricated in a l.O-pm doublc mctal CMOS process operates 16 nSec in thc worst caw of 70 "€2 and 4.75 volt power voltage.
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تاریخ انتشار 1993